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Classes</h2></td></tr>
<tr class="memitem:unionstandard__version__t"><td class="memItemLeft" align="right" valign="top">union &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspi__driver.html#unionstandard__version__t">standard_version_t</a></td></tr>
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<tr class="memitem:structstandard__version__t_8_b"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspi__driver.html#structstandard__version__t_8_b">standard_version_t.B</a></td></tr>
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<tr class="memitem:structqspi__config__t"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspi__driver.html#structqspi__config__t">SFLASH_CONFIGURATION_PARAM_PTR</a></td></tr>
<tr class="memdesc:structqspi__config__t"><td class="mdescLeft">&#160;</td><td class="mdescRight">QuadSPI Config block structure.  <a href="group__qspi__driver.html#structqspi__config__t">More...</a><br /></td></tr>
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Enumerations</h2></td></tr>
<tr class="memitem:gafe5d4eb1c09cf453dff43220b6a12703"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspi__driver.html#gafe5d4eb1c09cf453dff43220b6a12703">__qspi_config_block_tags</a> { <br />
&#160;&#160;<a class="el" href="group__qspi__driver.html#ggafe5d4eb1c09cf453dff43220b6a12703ac54a224f2e32adbbc6fb471c693cc27e">kQspiConfigTag</a> = FOUR_CHAR_CODE('k', 'q', 'c', 'f'), 
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&#160;&#160;<b>kQspiVersionTag</b> = FOUR_CHAR_CODE(0, 1, 1, 'Q')
<br />
 }</td></tr>
<tr class="separator:gafe5d4eb1c09cf453dff43220b6a12703"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga02f1188c182bdacfcea22e66919c6759"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspi__driver.html#ga02f1188c182bdacfcea22e66919c6759">qspiflash_mode_option_t</a> { <br />
&#160;&#160;<a class="el" href="group__qspi__driver.html#gga02f1188c182bdacfcea22e66919c6759ad127a926c5d34cc1da7b897270fa3936">kQspiFlashMode_Serial</a> = 0, 
<br />
&#160;&#160;<a class="el" href="group__qspi__driver.html#gga02f1188c182bdacfcea22e66919c6759af02a1e4ae16ecb0018f17ac9ade3c1ea">kQspiFlashMode_Parallel</a> = 1
<br />
 }<tr class="memdesc:ga02f1188c182bdacfcea22e66919c6759"><td class="mdescLeft">&#160;</td><td class="mdescRight">QSPI Flash mode options.  <a href="group__qspi__driver.html#ga02f1188c182bdacfcea22e66919c6759">More...</a><br /></td></tr>
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<tr class="memitem:ga1ea9651e0eca55cae9a374022ff766c9"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspi__driver.html#ga1ea9651e0eca55cae9a374022ff766c9">qspiflash_pad_t</a> { <br />
&#160;&#160;<a class="el" href="group__qspi__driver.html#gga1ea9651e0eca55cae9a374022ff766c9ad57eaa96587461c244ddf5fff21ab485">kQspiFlashPad_Single</a> = 0, 
<br />
&#160;&#160;<a class="el" href="group__qspi__driver.html#gga1ea9651e0eca55cae9a374022ff766c9ace1db470ba87b9cf358d0a116072e4b2">kQspiFlashPad_Dual</a> = 1, 
<br />
&#160;&#160;<a class="el" href="group__qspi__driver.html#gga1ea9651e0eca55cae9a374022ff766c9ad061152bfb2f7db55b12c4fa1876f6ce">kQspiFlashPad_Quad</a> = 2, 
<br />
&#160;&#160;<a class="el" href="group__qspi__driver.html#gga1ea9651e0eca55cae9a374022ff766c9a4a3310d6637f9545812cf6c804b15452">kQspiFlashPad_Octal</a> = 3
<br />
 }<tr class="memdesc:ga1ea9651e0eca55cae9a374022ff766c9"><td class="mdescLeft">&#160;</td><td class="mdescRight">External spi flash pad definition.  <a href="group__qspi__driver.html#ga1ea9651e0eca55cae9a374022ff766c9">More...</a><br /></td></tr>
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<tr class="separator:ga1ea9651e0eca55cae9a374022ff766c9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3cb2930eb063b8a0ee0d0ad6461185dc"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspi__driver.html#ga3cb2930eb063b8a0ee0d0ad6461185dc">qspi_serial_clock_freq_t</a> { <br />
&#160;&#160;<a class="el" href="group__qspi__driver.html#gga3cb2930eb063b8a0ee0d0ad6461185dcae5253546d3c63443dfc65b31b73ead05">kQspiSerialClockFreq_Low</a> = 0, 
<br />
&#160;&#160;<a class="el" href="group__qspi__driver.html#gga3cb2930eb063b8a0ee0d0ad6461185dca6bff6a7c4e62c14970831981b76e91bb">kQspiSerialClockFreq_Mid</a> = 1, 
<br />
&#160;&#160;<a class="el" href="group__qspi__driver.html#gga3cb2930eb063b8a0ee0d0ad6461185dca8495248acb7110dbdceba1320f411c92">kQspiSerialClockFreq_High</a> = 2
<br />
 }<tr class="memdesc:ga3cb2930eb063b8a0ee0d0ad6461185dc"><td class="mdescLeft">&#160;</td><td class="mdescRight">QSPI Serial Clock Frequency options.  <a href="group__qspi__driver.html#ga3cb2930eb063b8a0ee0d0ad6461185dc">More...</a><br /></td></tr>
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<tr class="separator:ga3cb2930eb063b8a0ee0d0ad6461185dc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga576461d7b38d5b13deca88af49c316c6"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspi__driver.html#ga576461d7b38d5b13deca88af49c316c6">qspi_port_enable_t</a> { <br />
&#160;&#160;<a class="el" href="group__qspi__driver.html#gga576461d7b38d5b13deca88af49c316c6a18a7922896000616fea087b277fa2a8d">kQspiPort_EnablePortA</a> = 0U, 
<br />
&#160;&#160;<a class="el" href="group__qspi__driver.html#gga576461d7b38d5b13deca88af49c316c6af164e49e9abdba0c40d79bf7cd97edf8">kQspiPort_EnableBothPorts</a> = 1
<br />
 }<tr class="memdesc:ga576461d7b38d5b13deca88af49c316c6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Port Enablement Option.  <a href="group__qspi__driver.html#ga576461d7b38d5b13deca88af49c316c6">More...</a><br /></td></tr>
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<tr class="separator:ga576461d7b38d5b13deca88af49c316c6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6698308aac86ad1fa3b7ffa8a98fb24d"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspi__driver.html#ga6698308aac86ad1fa3b7ffa8a98fb24d">qspi_ahb_data_transfer_size_t</a> { <br />
&#160;&#160;<a class="el" href="group__qspi__driver.html#gga6698308aac86ad1fa3b7ffa8a98fb24da79456c42f1ee632fe69e7895ec6c9879">kQspiAHBDataTransferSize_64Bytes</a> = 8U, 
<br />
&#160;&#160;<a class="el" href="group__qspi__driver.html#gga6698308aac86ad1fa3b7ffa8a98fb24da6fb67fc54308b9f33e03bcfeb0a4790e">kQspiAHBDataTransferSize_256Bytes</a> = 32U
<br />
 }<tr class="memdesc:ga6698308aac86ad1fa3b7ffa8a98fb24d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Definition for AHB data tranfer size.  <a href="group__qspi__driver.html#ga6698308aac86ad1fa3b7ffa8a98fb24d">More...</a><br /></td></tr>
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Functions</h2></td></tr>
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int&#160;</td><td class="memItemRight" valign="bottom"><b>main</b> (void)</td></tr>
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Variables</h2></td></tr>
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uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspi__driver.html#ga32afa1232ac14a96ec5c81cf186e17d5">standard_version_t::bugfix</a>: 8</td></tr>
<tr class="memdesc:ga32afa1232ac14a96ec5c81cf186e17d5"><td class="mdescLeft">&#160;</td><td class="mdescRight">bugfix version [7:0] <br /></td></tr>
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uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspi__driver.html#gad62a34b8bce33034cc477d86f116db3e">standard_version_t::minor</a>: 8</td></tr>
<tr class="memdesc:gad62a34b8bce33034cc477d86f116db3e"><td class="mdescLeft">&#160;</td><td class="mdescRight">minor version [15:8] <br /></td></tr>
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uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspi__driver.html#ga5a9d1cbe25a46d108ba8451e52e18939">standard_version_t::major</a>: 8</td></tr>
<tr class="memdesc:ga5a9d1cbe25a46d108ba8451e52e18939"><td class="mdescLeft">&#160;</td><td class="mdescRight">major version [23:16] <br /></td></tr>
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uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspi__driver.html#ga99c44be828a538d432dab6341315555f">standard_version_t::name</a>: 8</td></tr>
<tr class="memdesc:ga99c44be828a538d432dab6341315555f"><td class="mdescLeft">&#160;</td><td class="mdescRight">name [31:24] <br /></td></tr>
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<tr class="memitem:ga2e314036b944d74acaea48a08062000d"><td class="memItemLeft" ><a class="anchor" id="ga2e314036b944d74acaea48a08062000d"></a>
struct {</td></tr>
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uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspi__driver.html#ga32afa1232ac14a96ec5c81cf186e17d5">bugfix</a>: 8</td></tr>
<tr class="memdesc:ga32afa1232ac14a96ec5c81cf186e17d5"><td class="mdescLeft">&#160;</td><td class="mdescRight">bugfix version [7:0] <br /></td></tr>
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<tr class="memitem:gad62a34b8bce33034cc477d86f116db3e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gad62a34b8bce33034cc477d86f116db3e"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspi__driver.html#gad62a34b8bce33034cc477d86f116db3e">minor</a>: 8</td></tr>
<tr class="memdesc:gad62a34b8bce33034cc477d86f116db3e"><td class="mdescLeft">&#160;</td><td class="mdescRight">minor version [15:8] <br /></td></tr>
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uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspi__driver.html#ga5a9d1cbe25a46d108ba8451e52e18939">major</a>: 8</td></tr>
<tr class="memdesc:ga5a9d1cbe25a46d108ba8451e52e18939"><td class="mdescLeft">&#160;</td><td class="mdescRight">major version [23:16] <br /></td></tr>
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uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspi__driver.html#ga99c44be828a538d432dab6341315555f">name</a>: 8</td></tr>
<tr class="memdesc:ga99c44be828a538d432dab6341315555f"><td class="mdescLeft">&#160;</td><td class="mdescRight">name [31:24] <br /></td></tr>
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<tr class="memitem:ga2e314036b944d74acaea48a08062000d"><td class="memItemLeft" valign="top">}&#160;</td><td class="memItemRight" valign="bottom"><b>standard_version_t::B</b></td></tr>
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uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspi__driver.html#ga3dd1922cc6c81a38f435d39a64cd51c2">standard_version_t::version</a></td></tr>
<tr class="memdesc:ga3dd1922cc6c81a38f435d39a64cd51c2"><td class="mdescLeft">&#160;</td><td class="mdescRight">combined version numbers <br /></td></tr>
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uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspi__driver.html#gadc31f056f5b3b0310fb02a3c7c5ca54c">SFLASH_CONFIGURATION_PARAM_PTR::tag</a></td></tr>
<tr class="memdesc:gadc31f056f5b3b0310fb02a3c7c5ca54c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set to magic number of 'kqcf'. <br /></td></tr>
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<a class="el" href="group__qspi__driver.html#unionstandard__version__t">standard_version_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspi__driver.html#ga0b551621e1a210f66ae181397991d4c6">SFLASH_CONFIGURATION_PARAM_PTR::version</a></td></tr>
<tr class="memdesc:ga0b551621e1a210f66ae181397991d4c6"><td class="mdescLeft">&#160;</td><td class="mdescRight">version of config struct <br /></td></tr>
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uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspi__driver.html#ga95b21915032671ae2d2c6c65f9762f6b">SFLASH_CONFIGURATION_PARAM_PTR::lengthInBytes</a></td></tr>
<tr class="memdesc:ga95b21915032671ae2d2c6c65f9762f6b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Total length of strcut in bytes. <br /></td></tr>
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uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspi__driver.html#ga3fe022bbbc133cfaea562b1a31ef8a84">SFLASH_CONFIGURATION_PARAM_PTR::dqs_loopback</a></td></tr>
<tr class="memdesc:ga3fe022bbbc133cfaea562b1a31ef8a84"><td class="mdescLeft">&#160;</td><td class="mdescRight">Sets DQS LoopBack Mode to enable Dummy Pad MCR[24]. <br /></td></tr>
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uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspi__driver.html#gafb1bb6a70d97449a5677b3b9ae53324e">SFLASH_CONFIGURATION_PARAM_PTR::data_hold_time</a></td></tr>
<tr class="memdesc:gafb1bb6a70d97449a5677b3b9ae53324e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Serial Flash data hold time, valid value: 0/1/2. <br /></td></tr>
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uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspi__driver.html#ga88ff9220ba41e9883f46ac1e4bded6e5">SFLASH_CONFIGURATION_PARAM_PTR::reserved0</a> [2]</td></tr>
<tr class="memdesc:ga88ff9220ba41e9883f46ac1e4bded6e5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reserved for K80. <br /></td></tr>
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<tr class="memitem:ga770e525d25bdafc2af055a0a2b7982cb"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga770e525d25bdafc2af055a0a2b7982cb"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspi__driver.html#ga770e525d25bdafc2af055a0a2b7982cb">SFLASH_CONFIGURATION_PARAM_PTR::device_mode_config_en</a></td></tr>
<tr class="memdesc:ga770e525d25bdafc2af055a0a2b7982cb"><td class="mdescLeft">&#160;</td><td class="mdescRight">Determine if it is required to config working mode of external spi flash. <br /></td></tr>
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uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspi__driver.html#ga951d75c42aad01ce43200591d1b41e69">SFLASH_CONFIGURATION_PARAM_PTR::device_cmd</a></td></tr>
<tr class="memdesc:ga951d75c42aad01ce43200591d1b41e69"><td class="mdescLeft">&#160;</td><td class="mdescRight">Command to be tranferred to device. <br /></td></tr>
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uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspi__driver.html#ga1b1075d654ea4607544ebd4cc2236821">SFLASH_CONFIGURATION_PARAM_PTR::write_cmd_ipcr</a></td></tr>
<tr class="memdesc:ga1b1075d654ea4607544ebd4cc2236821"><td class="mdescLeft">&#160;</td><td class="mdescRight">IPCR value of Write command. <br /></td></tr>
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uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspi__driver.html#gad0afe559297c21f6bd6a8a4a7af8fcce">SFLASH_CONFIGURATION_PARAM_PTR::word_addressable</a></td></tr>
<tr class="memdesc:gad0afe559297c21f6bd6a8a4a7af8fcce"><td class="mdescLeft">&#160;</td><td class="mdescRight">Determine if the serial flash is word addressable. <br /></td></tr>
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uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspi__driver.html#ga1261cc21ab0230e84ee87dd3040c5dd7">SFLASH_CONFIGURATION_PARAM_PTR::cs_hold_time</a></td></tr>
<tr class="memdesc:ga1261cc21ab0230e84ee87dd3040c5dd7"><td class="mdescLeft">&#160;</td><td class="mdescRight">CS hold time in terms of serial clock.(for example 1 serial clock cyle) <br /></td></tr>
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uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspi__driver.html#ga40efa085b1fa43b63735d3769d22697e">SFLASH_CONFIGURATION_PARAM_PTR::cs_setup_time</a></td></tr>
<tr class="memdesc:ga40efa085b1fa43b63735d3769d22697e"><td class="mdescLeft">&#160;</td><td class="mdescRight">CS setup time in terms of serial clock.(for example 1 serial clock cyle) <br /></td></tr>
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uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspi__driver.html#gad202d16a4225bfa5bc0f4d1077ce965e">SFLASH_CONFIGURATION_PARAM_PTR::sflash_A1_size</a></td></tr>
<tr class="memdesc:gad202d16a4225bfa5bc0f4d1077ce965e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Size of flash connected on QSPI0A Ports and QSPI0A_SS0, in terms of Bytes. <br /></td></tr>
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uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspi__driver.html#ga3000582bf8696cff872214c449f13405">SFLASH_CONFIGURATION_PARAM_PTR::sflash_A2_size</a></td></tr>
<tr class="memdesc:ga3000582bf8696cff872214c449f13405"><td class="mdescLeft">&#160;</td><td class="mdescRight">Size of flash connected on QSPI0A Ports and QSPI0A_SS1, in terms of Bytes. <br /></td></tr>
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uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspi__driver.html#gafa690317ddd00683487f79fd18367bd5">SFLASH_CONFIGURATION_PARAM_PTR::sflash_B1_size</a></td></tr>
<tr class="memdesc:gafa690317ddd00683487f79fd18367bd5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Size of flash connected on QSPI0B Ports and QSPI0B_SS0, in terms of Bytes. <br /></td></tr>
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<tr class="memitem:ga0ffc08d0f6218b858c5aca1f0449bcf5"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga0ffc08d0f6218b858c5aca1f0449bcf5"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspi__driver.html#ga0ffc08d0f6218b858c5aca1f0449bcf5">SFLASH_CONFIGURATION_PARAM_PTR::sflash_B2_size</a></td></tr>
<tr class="memdesc:ga0ffc08d0f6218b858c5aca1f0449bcf5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Size of flash connected on QSPI0B Ports and QSPI0B_SS1, in terms of Bytes. <br /></td></tr>
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<tr class="memitem:gaaeffacfb4752666bed4a58bae161a85d"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaaeffacfb4752666bed4a58bae161a85d"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspi__driver.html#gaaeffacfb4752666bed4a58bae161a85d">SFLASH_CONFIGURATION_PARAM_PTR::sclk_freq</a></td></tr>
<tr class="memdesc:gaaeffacfb4752666bed4a58bae161a85d"><td class="mdescLeft">&#160;</td><td class="mdescRight">In 00 - 24MHz, 01 - 48MHz, 10 - 96MHz,(only for SDR Mode) <br /></td></tr>
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uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspi__driver.html#ga79f29c289ca84adc6fc424042a611fbe">SFLASH_CONFIGURATION_PARAM_PTR::busy_bit_offset</a></td></tr>
<tr class="memdesc:ga79f29c289ca84adc6fc424042a611fbe"><td class="mdescLeft">&#160;</td><td class="mdescRight">Flash device busy bit offset in status register. <br /></td></tr>
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uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspi__driver.html#ga9fa12614b6b0be127986256dbb368ff8">SFLASH_CONFIGURATION_PARAM_PTR::sflash_type</a></td></tr>
<tr class="memdesc:ga9fa12614b6b0be127986256dbb368ff8"><td class="mdescLeft">&#160;</td><td class="mdescRight">SPI flash type: 0-Single,1&ndash;Dual 2&ndash;Quad, 3&ndash; Octal. <br /></td></tr>
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<tr class="memitem:ga6105291e27f5dc10c568990e8bb989f3"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga6105291e27f5dc10c568990e8bb989f3"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspi__driver.html#ga6105291e27f5dc10c568990e8bb989f3">SFLASH_CONFIGURATION_PARAM_PTR::sflash_port</a></td></tr>
<tr class="memdesc:ga6105291e27f5dc10c568990e8bb989f3"><td class="mdescLeft">&#160;</td><td class="mdescRight">0&ndash;Only Port-A, 1&ndash;Both PortA and PortB <br /></td></tr>
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<tr class="memitem:ga918245d7c89e1e3460ec4ecc50527f67"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga918245d7c89e1e3460ec4ecc50527f67"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspi__driver.html#ga918245d7c89e1e3460ec4ecc50527f67">SFLASH_CONFIGURATION_PARAM_PTR::ddr_mode_enable</a></td></tr>
<tr class="memdesc:ga918245d7c89e1e3460ec4ecc50527f67"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable DDR mode if set to TRUE. <br /></td></tr>
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<tr class="memitem:gaa9b07235974d8f3d307f21dd000cc189"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaa9b07235974d8f3d307f21dd000cc189"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspi__driver.html#gaa9b07235974d8f3d307f21dd000cc189">SFLASH_CONFIGURATION_PARAM_PTR::dqs_enable</a></td></tr>
<tr class="memdesc:gaa9b07235974d8f3d307f21dd000cc189"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable DQS mode if set to TRUE. <br /></td></tr>
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<tr class="memitem:ga780fff717feeb8486b8bdee8fcf975a9"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga780fff717feeb8486b8bdee8fcf975a9"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspi__driver.html#ga780fff717feeb8486b8bdee8fcf975a9">SFLASH_CONFIGURATION_PARAM_PTR::parallel_mode_enable</a></td></tr>
<tr class="memdesc:ga780fff717feeb8486b8bdee8fcf975a9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable Individual or parrallel mode. <br /></td></tr>
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<tr class="memitem:gaf08cdaf72aa7700a58a4f934e35ba503"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaf08cdaf72aa7700a58a4f934e35ba503"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspi__driver.html#gaf08cdaf72aa7700a58a4f934e35ba503">SFLASH_CONFIGURATION_PARAM_PTR::portA_cs1</a></td></tr>
<tr class="memdesc:gaf08cdaf72aa7700a58a4f934e35ba503"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable PORTA CS1. <br /></td></tr>
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<tr class="memitem:gabb5da6fb469c138773e29f8354b7cd1a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gabb5da6fb469c138773e29f8354b7cd1a"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspi__driver.html#gabb5da6fb469c138773e29f8354b7cd1a">SFLASH_CONFIGURATION_PARAM_PTR::portB_cs1</a></td></tr>
<tr class="memdesc:gabb5da6fb469c138773e29f8354b7cd1a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable PORTB CS1. <br /></td></tr>
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<tr class="memitem:gab5c876c2ee99f8fc7d6fa4e2888dcf30"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gab5c876c2ee99f8fc7d6fa4e2888dcf30"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspi__driver.html#gab5c876c2ee99f8fc7d6fa4e2888dcf30">SFLASH_CONFIGURATION_PARAM_PTR::fsphs</a></td></tr>
<tr class="memdesc:gab5c876c2ee99f8fc7d6fa4e2888dcf30"><td class="mdescLeft">&#160;</td><td class="mdescRight">Full speed delay selection for SDR instructions. <br /></td></tr>
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uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspi__driver.html#ga9f3c298a9ed12ceffd109601189f67a8">SFLASH_CONFIGURATION_PARAM_PTR::fsdly</a></td></tr>
<tr class="memdesc:ga9f3c298a9ed12ceffd109601189f67a8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Full speed phase selection for SDR instructions. <br /></td></tr>
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<tr class="memitem:ga1d46ab7a2b09d59ed4f5c2aba33e0f10"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga1d46ab7a2b09d59ed4f5c2aba33e0f10"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspi__driver.html#ga1d46ab7a2b09d59ed4f5c2aba33e0f10">SFLASH_CONFIGURATION_PARAM_PTR::ddrsmp</a></td></tr>
<tr class="memdesc:ga1d46ab7a2b09d59ed4f5c2aba33e0f10"><td class="mdescLeft">&#160;</td><td class="mdescRight">Select the sampling point for incomming data when serial flash is in DDR mdoe. <br /></td></tr>
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<tr class="memitem:ga07c88bba2a96ab887706c8f4665046ea"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga07c88bba2a96ab887706c8f4665046ea"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspi__driver.html#ga07c88bba2a96ab887706c8f4665046ea">SFLASH_CONFIGURATION_PARAM_PTR::look_up_table</a> [QSPI_LUT_MAX_ENTRIES]</td></tr>
<tr class="memdesc:ga07c88bba2a96ab887706c8f4665046ea"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set of seq to perform optimum read on SFLASH as as per vendor SFLASH. <br /></td></tr>
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<tr class="memitem:ga57e0a059e2142f613c80a30a7dccb478"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga57e0a059e2142f613c80a30a7dccb478"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspi__driver.html#ga57e0a059e2142f613c80a30a7dccb478">SFLASH_CONFIGURATION_PARAM_PTR::column_address_space</a></td></tr>
<tr class="memdesc:ga57e0a059e2142f613c80a30a7dccb478"><td class="mdescLeft">&#160;</td><td class="mdescRight">The width of the column address. <br /></td></tr>
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<tr class="memitem:gad7451cad8e36ad52dd7d38915eac5a78"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gad7451cad8e36ad52dd7d38915eac5a78"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspi__driver.html#gad7451cad8e36ad52dd7d38915eac5a78">SFLASH_CONFIGURATION_PARAM_PTR::config_cmd_en</a></td></tr>
<tr class="memdesc:gad7451cad8e36ad52dd7d38915eac5a78"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable config commands. <br /></td></tr>
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uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspi__driver.html#ga66bcaaefc6278b94affe2c8517e85696">SFLASH_CONFIGURATION_PARAM_PTR::config_cmds</a> [QSPI_PRE_CMD_CNT]</td></tr>
<tr class="memdesc:ga66bcaaefc6278b94affe2c8517e85696"><td class="mdescLeft">&#160;</td><td class="mdescRight">Config comands, used to configure nor flash. <br /></td></tr>
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<tr class="memitem:ga1e09dd15f07ae331d903520e82117d81"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga1e09dd15f07ae331d903520e82117d81"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspi__driver.html#ga1e09dd15f07ae331d903520e82117d81">SFLASH_CONFIGURATION_PARAM_PTR::config_cmds_args</a> [QSPI_PRE_CMD_CNT]</td></tr>
<tr class="memdesc:ga1e09dd15f07ae331d903520e82117d81"><td class="mdescLeft">&#160;</td><td class="mdescRight">Config commands arguments. <br /></td></tr>
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uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspi__driver.html#ga54b84681700489423276b733844723a7">SFLASH_CONFIGURATION_PARAM_PTR::differential_clock_pin_enable</a></td></tr>
<tr class="memdesc:ga54b84681700489423276b733844723a7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Differential flash clock pins enable. <br /></td></tr>
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<tr class="memitem:ga05f821d775d5fa059ad4bea4896a56a3"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga05f821d775d5fa059ad4bea4896a56a3"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspi__driver.html#ga05f821d775d5fa059ad4bea4896a56a3">SFLASH_CONFIGURATION_PARAM_PTR::flash_CK2_clock_pin_enable</a></td></tr>
<tr class="memdesc:ga05f821d775d5fa059ad4bea4896a56a3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Flash CK2 clock pin enable. <br /></td></tr>
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<tr class="memitem:ga68a89467c3146f380358bb971e70eb51"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga68a89467c3146f380358bb971e70eb51"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspi__driver.html#ga68a89467c3146f380358bb971e70eb51">SFLASH_CONFIGURATION_PARAM_PTR::dqs_inverse_sel</a></td></tr>
<tr class="memdesc:ga68a89467c3146f380358bb971e70eb51"><td class="mdescLeft">&#160;</td><td class="mdescRight">Select clock source for internal DQS generation. <br /></td></tr>
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uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspi__driver.html#ga853583814254832235fe084b5b8bf12d">SFLASH_CONFIGURATION_PARAM_PTR::dqs_latency_enable</a></td></tr>
<tr class="memdesc:ga853583814254832235fe084b5b8bf12d"><td class="mdescLeft">&#160;</td><td class="mdescRight">DQS Latency Enable. <br /></td></tr>
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uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspi__driver.html#gaf1180634fbb3d0b9aa01a6bc3a0fd687">SFLASH_CONFIGURATION_PARAM_PTR::dqs_loopback_internal</a></td></tr>
<tr class="memdesc:gaf1180634fbb3d0b9aa01a6bc3a0fd687"><td class="mdescLeft">&#160;</td><td class="mdescRight">0: dqs loopback from pad, 1: dqs loopback internally <br /></td></tr>
<tr class="separator:gaf1180634fbb3d0b9aa01a6bc3a0fd687"><td class="memSeparator" colspan="2">&#160;</td></tr>
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uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspi__driver.html#ga544ee71f279e59d9743c1ad1e2185d57">SFLASH_CONFIGURATION_PARAM_PTR::dqs_phase_sel</a></td></tr>
<tr class="memdesc:ga544ee71f279e59d9743c1ad1e2185d57"><td class="mdescLeft">&#160;</td><td class="mdescRight">dqs phase sel <br /></td></tr>
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uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspi__driver.html#gaf743122d6d21455b281f52203c84ea8d">SFLASH_CONFIGURATION_PARAM_PTR::dqs_fa_delay_chain_sel</a></td></tr>
<tr class="memdesc:gaf743122d6d21455b281f52203c84ea8d"><td class="mdescLeft">&#160;</td><td class="mdescRight">dqs fa delay chain selection <br /></td></tr>
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<tr class="memitem:gaa27527eb4cfdde0458e649d9cac7ff79"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaa27527eb4cfdde0458e649d9cac7ff79"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspi__driver.html#gaa27527eb4cfdde0458e649d9cac7ff79">SFLASH_CONFIGURATION_PARAM_PTR::dqs_fb_delay_chain_sel</a></td></tr>
<tr class="memdesc:gaa27527eb4cfdde0458e649d9cac7ff79"><td class="mdescLeft">&#160;</td><td class="mdescRight">dqs fb delay chain selection <br /></td></tr>
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<tr class="memitem:gad5aa0c87f8c0f72779369f7e717cd858"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gad5aa0c87f8c0f72779369f7e717cd858"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspi__driver.html#gad5aa0c87f8c0f72779369f7e717cd858">SFLASH_CONFIGURATION_PARAM_PTR::reserved1</a> [2]</td></tr>
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uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspi__driver.html#ga2b94f530b0e69c522b2c9266ddb530bf">SFLASH_CONFIGURATION_PARAM_PTR::pagesize</a></td></tr>
<tr class="memdesc:ga2b94f530b0e69c522b2c9266ddb530bf"><td class="mdescLeft">&#160;</td><td class="mdescRight">page Size of Serial Flash <br /></td></tr>
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uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspi__driver.html#ga11194d3acd810424a6b7932f5ece6d57">SFLASH_CONFIGURATION_PARAM_PTR::sectorsize</a></td></tr>
<tr class="memdesc:ga11194d3acd810424a6b7932f5ece6d57"><td class="mdescLeft">&#160;</td><td class="mdescRight">sector Size of Serial Flash <br /></td></tr>
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<tr class="separator:ga2e4de71afa8b28668794e10dbf9494ea"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf8c2d757e533cf698c98da78d4cdcb88"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaf8c2d757e533cf698c98da78d4cdcb88"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspi__driver.html#gaf8c2d757e533cf698c98da78d4cdcb88">SFLASH_CONFIGURATION_PARAM_PTR::ips_command_second_divider</a></td></tr>
<tr class="memdesc:gaf8c2d757e533cf698c98da78d4cdcb88"><td class="mdescLeft">&#160;</td><td class="mdescRight">second devider for all IPS commands. <br /></td></tr>
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uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspi__driver.html#ga56fc812a7cd0f8bb742094100b9337e1">SFLASH_CONFIGURATION_PARAM_PTR::need_multi_phases</a></td></tr>
<tr class="memdesc:ga56fc812a7cd0f8bb742094100b9337e1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Determine if multiple hases command are needed. <br /></td></tr>
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<tr class="memitem:gabe1124a5208ff52c7d5d49132e638275"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gabe1124a5208ff52c7d5d49132e638275"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspi__driver.html#gabe1124a5208ff52c7d5d49132e638275">SFLASH_CONFIGURATION_PARAM_PTR::is_spansion_hyperflash</a></td></tr>
<tr class="memdesc:gabe1124a5208ff52c7d5d49132e638275"><td class="mdescLeft">&#160;</td><td class="mdescRight">Determine if connected spi flash device belongs to Hyperflash family. <br /></td></tr>
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uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspi__driver.html#ga55db027984603cf743246fe5c110e2d5">SFLASH_CONFIGURATION_PARAM_PTR::pre_read_status_cmd_address_offset</a></td></tr>
<tr class="memdesc:ga55db027984603cf743246fe5c110e2d5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Address for PreReadStatus command. <br /></td></tr>
<tr class="separator:ga55db027984603cf743246fe5c110e2d5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5d765458e55d90cc6f43c22128843d1c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga5d765458e55d90cc6f43c22128843d1c"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspi__driver.html#ga5d765458e55d90cc6f43c22128843d1c">SFLASH_CONFIGURATION_PARAM_PTR::pre_unlock_cmd_address_offset</a></td></tr>
<tr class="memdesc:ga5d765458e55d90cc6f43c22128843d1c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Address for PreWriteEnable command. <br /></td></tr>
<tr class="separator:ga5d765458e55d90cc6f43c22128843d1c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5cfdc24a655280f6eac98ea5f6a6b076"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga5cfdc24a655280f6eac98ea5f6a6b076"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspi__driver.html#ga5cfdc24a655280f6eac98ea5f6a6b076">SFLASH_CONFIGURATION_PARAM_PTR::unlock_cmd_address_offset</a></td></tr>
<tr class="memdesc:ga5cfdc24a655280f6eac98ea5f6a6b076"><td class="mdescLeft">&#160;</td><td class="mdescRight">Address for WriteEnable command. <br /></td></tr>
<tr class="separator:ga5cfdc24a655280f6eac98ea5f6a6b076"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga530f8d72cbfd0dafb19efed652b64888"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga530f8d72cbfd0dafb19efed652b64888"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspi__driver.html#ga530f8d72cbfd0dafb19efed652b64888">SFLASH_CONFIGURATION_PARAM_PTR::pre_program_cmd_address_offset</a></td></tr>
<tr class="memdesc:ga530f8d72cbfd0dafb19efed652b64888"><td class="mdescLeft">&#160;</td><td class="mdescRight">Address for PreProgram command. <br /></td></tr>
<tr class="separator:ga530f8d72cbfd0dafb19efed652b64888"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad0a2bb7d2f1013637ff6e5540cf5fe2a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gad0a2bb7d2f1013637ff6e5540cf5fe2a"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspi__driver.html#gad0a2bb7d2f1013637ff6e5540cf5fe2a">SFLASH_CONFIGURATION_PARAM_PTR::pre_erase_cmd_address_offset</a></td></tr>
<tr class="memdesc:gad0a2bb7d2f1013637ff6e5540cf5fe2a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Address for PreErase command. <br /></td></tr>
<tr class="separator:gad0a2bb7d2f1013637ff6e5540cf5fe2a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae4c169976be1c5f72ad402340c12659a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gae4c169976be1c5f72ad402340c12659a"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspi__driver.html#gae4c169976be1c5f72ad402340c12659a">SFLASH_CONFIGURATION_PARAM_PTR::erase_all_cmd_address_offset</a></td></tr>
<tr class="memdesc:gae4c169976be1c5f72ad402340c12659a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Address for EraseAll command. <br /></td></tr>
<tr class="separator:gae4c169976be1c5f72ad402340c12659a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga655c7e35c2cfec5b6c6598f292a3f734"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga655c7e35c2cfec5b6c6598f292a3f734"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspi__driver.html#ga655c7e35c2cfec5b6c6598f292a3f734">SFLASH_CONFIGURATION_PARAM_PTR::reserved2</a> [3]</td></tr>
<tr class="memdesc:ga655c7e35c2cfec5b6c6598f292a3f734"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reserved words to make sure qspi config block is page-aligend. <br /></td></tr>
<tr class="separator:ga655c7e35c2cfec5b6c6598f292a3f734"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table>
<a name="details" id="details"></a><h2 class="groupheader">Usage Information</h2>
<hr/><h2 class="groupheader">Class Documentation</h2>
<a name="unionstandard__version__t" id="unionstandard__version__t"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">union standard_version_t</td>
        </tr>
      </table>
</div><div class="memdoc">
<div class="textblock"></div><table class="fieldtable">
<tr><th colspan="3">Class Members</th></tr>
<tr><td class="fieldtype">
<a class="anchor" id="ga2e314036b944d74acaea48a08062000d"></a>struct <a class="el" href="group__qspi__driver.html#structstandard__version__t_8_b">standard_version_t</a></td>
<td class="fieldname">
B</td>
<td class="fielddoc">
</td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="ga3dd1922cc6c81a38f435d39a64cd51c2"></a>uint32_t</td>
<td class="fieldname">
version</td>
<td class="fielddoc">
combined version numbers </td></tr>
</table>

</div>
</div>
<a name="structstandard__version__t_8_b" id="structstandard__version__t_8_b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">struct standard_version_t.B</td>
        </tr>
      </table>
</div><div class="memdoc">
<div class="textblock"></div><table class="fieldtable">
<tr><th colspan="3">Class Members</th></tr>
<tr><td class="fieldtype">
<a class="anchor" id="a35eaed2063b729088b47a7d36ba6567f"></a>uint32_t</td>
<td class="fieldname">
bugfix: 8</td>
<td class="fielddoc">
bugfix version [7:0] </td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="af1425da40a9f2d21ab702a1c7feae026"></a>uint32_t</td>
<td class="fieldname">
major: 8</td>
<td class="fielddoc">
major version [23:16] </td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="aab846c0e3717a3e7d14af45cab70b44a"></a>uint32_t</td>
<td class="fieldname">
minor: 8</td>
<td class="fielddoc">
minor version [15:8] </td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="ab068931cc450442b63f5b3d276ea4297"></a>uint32_t</td>
<td class="fieldname">
name: 8</td>
<td class="fielddoc">
name [31:24] </td></tr>
</table>

</div>
</div>
<a name="structqspi__config__t" id="structqspi__config__t"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">struct qspi_config_t</td>
        </tr>
      </table>
</div><div class="memdoc">
<div class="textblock"><p>QuadSPI Config block structure. </p>
</div><div id="dynsection-0" onclick="return toggleVisibility(this)" class="dynheader closed" style="cursor:pointer;">
  <img id="dynsection-0-trigger" src="closed.png" alt="+"/> Collaboration diagram for SFLASH_CONFIGURATION_PARAM_PTR:</div>
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</div>
<div id="dynsection-0-content" class="dyncontent" style="display:none;">
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</div>
<center><span class="legend">[<a target="top" href="graph_legend.html">legend</a>]</span></center></div>
<table class="fieldtable">
<tr><th colspan="3">Class Members</th></tr>
<tr><td class="fieldtype">
<a class="anchor" id="ga79f29c289ca84adc6fc424042a611fbe"></a>uint32_t</td>
<td class="fieldname">
busy_bit_offset</td>
<td class="fielddoc">
Flash device busy bit offset in status register. </td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="ga57e0a059e2142f613c80a30a7dccb478"></a>uint32_t</td>
<td class="fieldname">
column_address_space</td>
<td class="fielddoc">
The width of the column address. </td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="gad7451cad8e36ad52dd7d38915eac5a78"></a>uint32_t</td>
<td class="fieldname">
config_cmd_en</td>
<td class="fielddoc">
Enable config commands. </td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="ga66bcaaefc6278b94affe2c8517e85696"></a>uint32_t</td>
<td class="fieldname">
config_cmds[QSPI_PRE_CMD_CNT]</td>
<td class="fielddoc">
Config comands, used to configure nor flash. </td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="ga1e09dd15f07ae331d903520e82117d81"></a>uint32_t</td>
<td class="fieldname">
config_cmds_args[QSPI_PRE_CMD_CNT]</td>
<td class="fielddoc">
Config commands arguments. </td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="ga1261cc21ab0230e84ee87dd3040c5dd7"></a>uint32_t</td>
<td class="fieldname">
cs_hold_time</td>
<td class="fielddoc">
CS hold time in terms of serial clock.(for example 1 serial clock cyle) </td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="ga40efa085b1fa43b63735d3769d22697e"></a>uint32_t</td>
<td class="fieldname">
cs_setup_time</td>
<td class="fielddoc">
CS setup time in terms of serial clock.(for example 1 serial clock cyle) </td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="gafb1bb6a70d97449a5677b3b9ae53324e"></a>uint32_t</td>
<td class="fieldname">
data_hold_time</td>
<td class="fielddoc">
Serial Flash data hold time, valid value: 0/1/2. </td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="ga918245d7c89e1e3460ec4ecc50527f67"></a>uint32_t</td>
<td class="fieldname">
ddr_mode_enable</td>
<td class="fielddoc">
Enable DDR mode if set to TRUE. </td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="ga1d46ab7a2b09d59ed4f5c2aba33e0f10"></a>uint32_t</td>
<td class="fieldname">
ddrsmp</td>
<td class="fielddoc">
Select the sampling point for incomming data when serial flash is in DDR mdoe. </td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="ga951d75c42aad01ce43200591d1b41e69"></a>uint32_t</td>
<td class="fieldname">
device_cmd</td>
<td class="fielddoc">
Command to be tranferred to device. </td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="ga770e525d25bdafc2af055a0a2b7982cb"></a>uint32_t</td>
<td class="fieldname">
device_mode_config_en</td>
<td class="fielddoc">
Determine if it is required to config working mode of external spi flash. </td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="ga54b84681700489423276b733844723a7"></a>uint32_t</td>
<td class="fieldname">
differential_clock_pin_enable</td>
<td class="fielddoc">
Differential flash clock pins enable. </td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="gaa9b07235974d8f3d307f21dd000cc189"></a>uint32_t</td>
<td class="fieldname">
dqs_enable</td>
<td class="fielddoc">
Enable DQS mode if set to TRUE. </td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="gaf743122d6d21455b281f52203c84ea8d"></a>uint32_t</td>
<td class="fieldname">
dqs_fa_delay_chain_sel</td>
<td class="fielddoc">
dqs fa delay chain selection </td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="gaa27527eb4cfdde0458e649d9cac7ff79"></a>uint32_t</td>
<td class="fieldname">
dqs_fb_delay_chain_sel</td>
<td class="fielddoc">
dqs fb delay chain selection </td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="ga68a89467c3146f380358bb971e70eb51"></a>uint32_t</td>
<td class="fieldname">
dqs_inverse_sel</td>
<td class="fielddoc">
Select clock source for internal DQS generation. </td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="ga853583814254832235fe084b5b8bf12d"></a>uint32_t</td>
<td class="fieldname">
dqs_latency_enable</td>
<td class="fielddoc">
DQS Latency Enable. </td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="ga3fe022bbbc133cfaea562b1a31ef8a84"></a>uint32_t</td>
<td class="fieldname">
dqs_loopback</td>
<td class="fielddoc">
Sets DQS LoopBack Mode to enable Dummy Pad MCR[24]. </td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="gaf1180634fbb3d0b9aa01a6bc3a0fd687"></a>uint32_t</td>
<td class="fieldname">
dqs_loopback_internal</td>
<td class="fielddoc">
0: dqs loopback from pad, 1: dqs loopback internally </td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="ga544ee71f279e59d9743c1ad1e2185d57"></a>uint32_t</td>
<td class="fieldname">
dqs_phase_sel</td>
<td class="fielddoc">
dqs phase sel </td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="gae4c169976be1c5f72ad402340c12659a"></a>uint32_t</td>
<td class="fieldname">
erase_all_cmd_address_offset</td>
<td class="fielddoc">
Address for EraseAll command. </td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="ga05f821d775d5fa059ad4bea4896a56a3"></a>uint32_t</td>
<td class="fieldname">
flash_CK2_clock_pin_enable</td>
<td class="fielddoc">
Flash CK2 clock pin enable. </td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="ga9f3c298a9ed12ceffd109601189f67a8"></a>uint32_t</td>
<td class="fieldname">
fsdly</td>
<td class="fielddoc">
Full speed phase selection for SDR instructions. </td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="gab5c876c2ee99f8fc7d6fa4e2888dcf30"></a>uint32_t</td>
<td class="fieldname">
fsphs</td>
<td class="fielddoc">
Full speed delay selection for SDR instructions. </td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="gaf8c2d757e533cf698c98da78d4cdcb88"></a>uint32_t</td>
<td class="fieldname">
ips_command_second_divider</td>
<td class="fielddoc">
second devider for all IPS commands. </td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="gabe1124a5208ff52c7d5d49132e638275"></a>uint32_t</td>
<td class="fieldname">
is_spansion_hyperflash</td>
<td class="fielddoc">
Determine if connected spi flash device belongs to Hyperflash family. </td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="ga95b21915032671ae2d2c6c65f9762f6b"></a>uint32_t</td>
<td class="fieldname">
lengthInBytes</td>
<td class="fielddoc">
Total length of strcut in bytes. </td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="ga07c88bba2a96ab887706c8f4665046ea"></a>uint32_t</td>
<td class="fieldname">
look_up_table[QSPI_LUT_MAX_ENTRIES]</td>
<td class="fielddoc">
Set of seq to perform optimum read on SFLASH as as per vendor SFLASH. </td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="ga56fc812a7cd0f8bb742094100b9337e1"></a>uint32_t</td>
<td class="fieldname">
need_multi_phases</td>
<td class="fielddoc">
Determine if multiple hases command are needed. </td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="ga2b94f530b0e69c522b2c9266ddb530bf"></a>uint32_t</td>
<td class="fieldname">
pagesize</td>
<td class="fielddoc">
page Size of Serial Flash </td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="ga780fff717feeb8486b8bdee8fcf975a9"></a>uint32_t</td>
<td class="fieldname">
parallel_mode_enable</td>
<td class="fielddoc">
Enable Individual or parrallel mode. </td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="gaf08cdaf72aa7700a58a4f934e35ba503"></a>uint32_t</td>
<td class="fieldname">
portA_cs1</td>
<td class="fielddoc">
Enable PORTA CS1. </td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="gabb5da6fb469c138773e29f8354b7cd1a"></a>uint32_t</td>
<td class="fieldname">
portB_cs1</td>
<td class="fielddoc">
Enable PORTB CS1. </td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="gad0a2bb7d2f1013637ff6e5540cf5fe2a"></a>uint32_t</td>
<td class="fieldname">
pre_erase_cmd_address_offset</td>
<td class="fielddoc">
Address for PreErase command. </td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="ga530f8d72cbfd0dafb19efed652b64888"></a>uint32_t</td>
<td class="fieldname">
pre_program_cmd_address_offset</td>
<td class="fielddoc">
Address for PreProgram command. </td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="ga55db027984603cf743246fe5c110e2d5"></a>uint32_t</td>
<td class="fieldname">
pre_read_status_cmd_address_offset</td>
<td class="fielddoc">
Address for PreReadStatus command. </td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="ga5d765458e55d90cc6f43c22128843d1c"></a>uint32_t</td>
<td class="fieldname">
pre_unlock_cmd_address_offset</td>
<td class="fielddoc">
Address for PreWriteEnable command. </td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="ga88ff9220ba41e9883f46ac1e4bded6e5"></a>uint32_t</td>
<td class="fieldname">
reserved0[2]</td>
<td class="fielddoc">
Reserved for K80. </td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="gad5aa0c87f8c0f72779369f7e717cd858"></a>uint32_t</td>
<td class="fieldname">
reserved1[2]</td>
<td class="fielddoc">
reserved </td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="ga655c7e35c2cfec5b6c6598f292a3f734"></a>uint32_t</td>
<td class="fieldname">
reserved2[3]</td>
<td class="fielddoc">
Reserved words to make sure qspi config block is page-aligend. </td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="gaaeffacfb4752666bed4a58bae161a85d"></a>uint32_t</td>
<td class="fieldname">
sclk_freq</td>
<td class="fielddoc">
In 00 - 24MHz, 01 - 48MHz, 10 - 96MHz,(only for SDR Mode) </td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="ga11194d3acd810424a6b7932f5ece6d57"></a>uint32_t</td>
<td class="fieldname">
sectorsize</td>
<td class="fielddoc">
sector Size of Serial Flash </td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="gad202d16a4225bfa5bc0f4d1077ce965e"></a>uint32_t</td>
<td class="fieldname">
sflash_A1_size</td>
<td class="fielddoc">
Size of flash connected on QSPI0A Ports and QSPI0A_SS0, in terms of Bytes. </td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="ga3000582bf8696cff872214c449f13405"></a>uint32_t</td>
<td class="fieldname">
sflash_A2_size</td>
<td class="fielddoc">
Size of flash connected on QSPI0A Ports and QSPI0A_SS1, in terms of Bytes. </td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="gafa690317ddd00683487f79fd18367bd5"></a>uint32_t</td>
<td class="fieldname">
sflash_B1_size</td>
<td class="fielddoc">
Size of flash connected on QSPI0B Ports and QSPI0B_SS0, in terms of Bytes. </td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="ga0ffc08d0f6218b858c5aca1f0449bcf5"></a>uint32_t</td>
<td class="fieldname">
sflash_B2_size</td>
<td class="fielddoc">
Size of flash connected on QSPI0B Ports and QSPI0B_SS1, in terms of Bytes. </td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="ga6105291e27f5dc10c568990e8bb989f3"></a>uint32_t</td>
<td class="fieldname">
sflash_port</td>
<td class="fielddoc">
0&ndash;Only Port-A, 1&ndash;Both PortA and PortB </td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="ga9fa12614b6b0be127986256dbb368ff8"></a>uint32_t</td>
<td class="fieldname">
sflash_type</td>
<td class="fielddoc">
SPI flash type: 0-Single,1&ndash;Dual 2&ndash;Quad, 3&ndash; Octal. </td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="gadc31f056f5b3b0310fb02a3c7c5ca54c"></a>uint32_t</td>
<td class="fieldname">
tag</td>
<td class="fielddoc">
Set to magic number of 'kqcf'. </td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="ga2e4de71afa8b28668794e10dbf9494ea"></a>uint32_t</td>
<td class="fieldname">
timeout_milliseconds</td>
<td class="fielddoc">
<p>timeout in terms of millisecond in case of infinite loop in qspi driver 0 represents disabling timeout check. This value is valid since version 1.1.0 </p>
</td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="ga5cfdc24a655280f6eac98ea5f6a6b076"></a>uint32_t</td>
<td class="fieldname">
unlock_cmd_address_offset</td>
<td class="fielddoc">
Address for WriteEnable command. </td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="ga0b551621e1a210f66ae181397991d4c6"></a><a class="el" href="group__qspi__driver.html#unionstandard__version__t">standard_version_t</a></td>
<td class="fieldname">
version</td>
<td class="fielddoc">
version of config struct </td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="gad0afe559297c21f6bd6a8a4a7af8fcce"></a>uint32_t</td>
<td class="fieldname">
word_addressable</td>
<td class="fielddoc">
Determine if the serial flash is word addressable. </td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="ga1b1075d654ea4607544ebd4cc2236821"></a>uint32_t</td>
<td class="fieldname">
write_cmd_ipcr</td>
<td class="fielddoc">
IPCR value of Write command. </td></tr>
</table>

</div>
</div>
<h2 class="groupheader">Enumeration Type Documentation</h2>
<a class="anchor" id="gafe5d4eb1c09cf453dff43220b6a12703"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">enum <a class="el" href="group__qspi__driver.html#gafe5d4eb1c09cf453dff43220b6a12703">__qspi_config_block_tags</a></td>
        </tr>
      </table>
</div><div class="memdoc">
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a class="anchor" id="ggafe5d4eb1c09cf453dff43220b6a12703ac54a224f2e32adbbc6fb471c693cc27e"></a>kQspiConfigTag&#160;</td><td class="fielddoc">
<p>Tag value used to validate the qspi config block. </p>
</td></tr>
</table>

</div>
</div>
<a class="anchor" id="ga6698308aac86ad1fa3b7ffa8a98fb24d"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">enum <a class="el" href="group__qspi__driver.html#ga6698308aac86ad1fa3b7ffa8a98fb24d">qspi_ahb_data_transfer_size_t</a></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Definition for AHB data tranfer size. </p>
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a class="anchor" id="gga6698308aac86ad1fa3b7ffa8a98fb24da79456c42f1ee632fe69e7895ec6c9879"></a>kQspiAHBDataTransferSize_64Bytes&#160;</td><td class="fielddoc">
<p>AHB data transfer size is 64bytes. </p>
</td></tr>
<tr><td class="fieldname"><a class="anchor" id="gga6698308aac86ad1fa3b7ffa8a98fb24da6fb67fc54308b9f33e03bcfeb0a4790e"></a>kQspiAHBDataTransferSize_256Bytes&#160;</td><td class="fielddoc">
<p>AHB data transfer size is 256bytes. </p>
</td></tr>
</table>

</div>
</div>
<a class="anchor" id="ga576461d7b38d5b13deca88af49c316c6"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">enum <a class="el" href="group__qspi__driver.html#ga576461d7b38d5b13deca88af49c316c6">qspi_port_enable_t</a></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Port Enablement Option. </p>
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a class="anchor" id="gga576461d7b38d5b13deca88af49c316c6a18a7922896000616fea087b277fa2a8d"></a>kQspiPort_EnablePortA&#160;</td><td class="fielddoc">
<p>Only PORTA is enabled. </p>
</td></tr>
<tr><td class="fieldname"><a class="anchor" id="gga576461d7b38d5b13deca88af49c316c6af164e49e9abdba0c40d79bf7cd97edf8"></a>kQspiPort_EnableBothPorts&#160;</td><td class="fielddoc">
<p>Enable Both PoartA and PortB. </p>
</td></tr>
</table>

</div>
</div>
<a class="anchor" id="ga3cb2930eb063b8a0ee0d0ad6461185dc"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">enum <a class="el" href="group__qspi__driver.html#ga3cb2930eb063b8a0ee0d0ad6461185dc">qspi_serial_clock_freq_t</a></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>QSPI Serial Clock Frequency options. </p>
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a class="anchor" id="gga3cb2930eb063b8a0ee0d0ad6461185dcae5253546d3c63443dfc65b31b73ead05"></a>kQspiSerialClockFreq_Low&#160;</td><td class="fielddoc">
<p>QuadSPI module works at low frequency. </p>
</td></tr>
<tr><td class="fieldname"><a class="anchor" id="gga3cb2930eb063b8a0ee0d0ad6461185dca6bff6a7c4e62c14970831981b76e91bb"></a>kQspiSerialClockFreq_Mid&#160;</td><td class="fielddoc">
<p>QuadSPI module works at mid frequency. </p>
</td></tr>
<tr><td class="fieldname"><a class="anchor" id="gga3cb2930eb063b8a0ee0d0ad6461185dca8495248acb7110dbdceba1320f411c92"></a>kQspiSerialClockFreq_High&#160;</td><td class="fielddoc">
<p>QuadSPI module works at high frequency. </p>
</td></tr>
</table>

</div>
</div>
<a class="anchor" id="ga02f1188c182bdacfcea22e66919c6759"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">enum <a class="el" href="group__qspi__driver.html#ga02f1188c182bdacfcea22e66919c6759">qspiflash_mode_option_t</a></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>QSPI Flash mode options. </p>
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a class="anchor" id="gga02f1188c182bdacfcea22e66919c6759ad127a926c5d34cc1da7b897270fa3936"></a>kQspiFlashMode_Serial&#160;</td><td class="fielddoc">
<p>Serial mode. </p>
</td></tr>
<tr><td class="fieldname"><a class="anchor" id="gga02f1188c182bdacfcea22e66919c6759af02a1e4ae16ecb0018f17ac9ade3c1ea"></a>kQspiFlashMode_Parallel&#160;</td><td class="fielddoc">
<p>Parallel mode. </p>
</td></tr>
</table>

</div>
</div>
<a class="anchor" id="ga1ea9651e0eca55cae9a374022ff766c9"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">enum <a class="el" href="group__qspi__driver.html#ga1ea9651e0eca55cae9a374022ff766c9">qspiflash_pad_t</a></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>External spi flash pad definition. </p>
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a class="anchor" id="gga1ea9651e0eca55cae9a374022ff766c9ad57eaa96587461c244ddf5fff21ab485"></a>kQspiFlashPad_Single&#160;</td><td class="fielddoc">
<p>Single-pad spi flash. </p>
</td></tr>
<tr><td class="fieldname"><a class="anchor" id="gga1ea9651e0eca55cae9a374022ff766c9ace1db470ba87b9cf358d0a116072e4b2"></a>kQspiFlashPad_Dual&#160;</td><td class="fielddoc">
<p>Dual-pad spi flash. </p>
</td></tr>
<tr><td class="fieldname"><a class="anchor" id="gga1ea9651e0eca55cae9a374022ff766c9ad061152bfb2f7db55b12c4fa1876f6ce"></a>kQspiFlashPad_Quad&#160;</td><td class="fielddoc">
<p>Quad-pad spi flash. </p>
</td></tr>
<tr><td class="fieldname"><a class="anchor" id="gga1ea9651e0eca55cae9a374022ff766c9a4a3310d6637f9545812cf6c804b15452"></a>kQspiFlashPad_Octal&#160;</td><td class="fielddoc">
<p>Octal-pad spi flash. </p>
</td></tr>
</table>

</div>
</div>
<h2 class="groupheader">Variable Documentation</h2>
<a class="anchor" id="ga2e314036b944d74acaea48a08062000d"></a>
<div class="memitem">
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        <tr>
          <td class="memname">struct { ... }   standard_version_t::B</td>
        </tr>
      </table>
</div><div class="memdoc">

</div>
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<p>bugfix version [7:0] </p>

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<p>Flash device busy bit offset in status register. </p>

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<p>The width of the column address. </p>

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<p>Enable config commands. </p>

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<p>Config comands, used to configure nor flash. </p>

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<p>Config commands arguments. </p>

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<p>CS hold time in terms of serial clock.(for example 1 serial clock cyle) </p>

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<p>CS setup time in terms of serial clock.(for example 1 serial clock cyle) </p>

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<p>Serial Flash data hold time, valid value: 0/1/2. </p>

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<p>Enable DDR mode if set to TRUE. </p>

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<p>Select the sampling point for incomming data when serial flash is in DDR mdoe. </p>

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<p>Command to be tranferred to device. </p>

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<p>Determine if it is required to config working mode of external spi flash. </p>

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<p>Differential flash clock pins enable. </p>

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<p>Enable DQS mode if set to TRUE. </p>

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<p>dqs fa delay chain selection </p>

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<p>dqs fb delay chain selection </p>

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<p>Select clock source for internal DQS generation. </p>

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<p>DQS Latency Enable. </p>

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<p>Sets DQS LoopBack Mode to enable Dummy Pad MCR[24]. </p>

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<p>0: dqs loopback from pad, 1: dqs loopback internally </p>

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<p>dqs phase sel </p>

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<p>Address for EraseAll command. </p>

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<p>Flash CK2 clock pin enable. </p>

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<p>Full speed phase selection for SDR instructions. </p>

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<p>Full speed delay selection for SDR instructions. </p>

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<p>second devider for all IPS commands. </p>

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<p>Determine if connected spi flash device belongs to Hyperflash family. </p>

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<p>Total length of strcut in bytes. </p>

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<p>Set of seq to perform optimum read on SFLASH as as per vendor SFLASH. </p>

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<p>major version [23:16] </p>

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<p>minor version [15:8] </p>

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<p>name [31:24] </p>

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<p>Determine if multiple hases command are needed. </p>

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<p>page Size of Serial Flash </p>

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<p>Enable Individual or parrallel mode. </p>

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<p>Enable PORTA CS1. </p>

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<p>Enable PORTB CS1. </p>

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<p>Address for PreErase command. </p>

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<p>Address for PreProgram command. </p>

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<p>Address for PreReadStatus command. </p>

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<p>Address for PreWriteEnable command. </p>

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<p>Reserved for K80. </p>

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<p>reserved </p>

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<p>Reserved words to make sure qspi config block is page-aligend. </p>

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<p>In 00 - 24MHz, 01 - 48MHz, 10 - 96MHz,(only for SDR Mode) </p>

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<p>sector Size of Serial Flash </p>

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<p>Size of flash connected on QSPI0A Ports and QSPI0A_SS0, in terms of Bytes. </p>

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<p>Size of flash connected on QSPI0A Ports and QSPI0A_SS1, in terms of Bytes. </p>

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<p>Size of flash connected on QSPI0B Ports and QSPI0B_SS0, in terms of Bytes. </p>

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<p>Size of flash connected on QSPI0B Ports and QSPI0B_SS1, in terms of Bytes. </p>

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<p>0&ndash;Only Port-A, 1&ndash;Both PortA and PortB </p>

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<p>SPI flash type: 0-Single,1&ndash;Dual 2&ndash;Quad, 3&ndash; Octal. </p>

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<p>Set to magic number of 'kqcf'. </p>

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<p>timeout in terms of millisecond in case of infinite loop in qspi driver 0 represents disabling timeout check. This value is valid since version 1.1.0 </p>

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<p>Address for WriteEnable command. </p>

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<p>combined version numbers </p>

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<p>version of config struct </p>

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<p>Determine if the serial flash is word addressable. </p>

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<p>IPCR value of Write command. </p>

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